1. Field of the Invention
This invention generally relates to digital flip-flop circuits, and more particularly to a binary flip-flop with enhanced support for dynamic circuit operations.
2. Description of the Related Art
In dynamic logic circuits, generally two phases are used in order to establish the correct signal at a logic node. During the first phase, the logic node is generally precharged to a high voltage and during the second phase the node is selectively discharged by providing an input signal to a discharge control node. The input signal can normally not be applied to the discharge control node until after the precharge phase is complete. Furthermore, if the input signal is unstable and changes its state after being applied to the discharge control node, that change of state can cause incorrect operation of the circuit. Thus, to provide proper timing control for the dynamic node, it becomes necessary to block the input signal from the discharge control node until the signal has resolved to a quiescent state so as to enable a sampling circuit to obtain the correct signal values.
Digital flip-flops are extensively used as building blocks in various logic designs. The foregoing discussion applies equally to the outputs of flip-flops when those outputs are also used as inputs in dynamic circuit operations. Thus, signals originating from a flip-flop, a timing signal is often required to block those signals until the flip-flop has stabilized its outputs to a predetermined quiescent state and after precharge is complete. FIG. 1 is a representative circuit depicting an arrangement to qualify the outputs of a flip-flop through use of an external ENABLE signal before those outputs are applied as inputs to a dynamic logic function.
In the depicted circuit, the ENABLE signal blocks the flip-flop outputs Q and QX during a possibly unstable period when a transition in the clock signal occurs. The Q output is shown applied as an input to a NAND gate 12 and its complement QX is shown applied to another NAND gate 14. The ENABLE signal is shown applied as an input to both NAND gates, 12 and 14, simultaneously. An associated signal flow diagram is shown in FIG. 2. In the timing diagram of FIG. 2, the outputs Q and QX are shown changing their states from low to high and high to low respectively after the rising edge of the clock signal applied to the CLK input node of the data flip-flop 10. Until the ENABLE signal is asserted, both outputs Q.sub.-- ENA and QX.sub.-- ENA in FIG. 1 are forced low. Only after the Q and QX outputs of the flip-flop have resolved to their quiescent state does the ENABLE input gate Q and QX to Q.sub.-- ENA and QX.sub.-- ENA respectively. These gated outputs Q.sub.-- ENA and QX.sub.-- ENA, in turn, can be applied as inputs to a subsequent dynamic logic function.
An example of a circuit requiring this gating through an external ENABLE signal would be a dynamic NOR gate used in zero detection. FIG. 3 shows an N-bit zero detection circuit built with conventional flip-flops generally represented by numeral 10 in FIGS. 1 and 3. Other elements constituting this circuit include a pair of delay inverters 20, an N number of AND gates 22--one for each flip-flop output bit, a corresponding N number of pull-down transistors 26 and a precharge transistor 24. In normal operation of this circuit, the ALL.sub.-- ZERO output line would be high when each flip-flop output bit, BIT.sub.-- 0 through BIT.sub.-- N, is "zero" or low. If any one of the output bits, i.e. BIT.sub.-- 0 through BIT.sub.-- N, changes its state from high to low and if this state change is allowed to propagate to the corresponding pull-down transistor 26 (i.e., if no enable signal were provided), then the prior high value may turn on the corresponding transistor 26 and, thus, may erroneously discharge the precharged D.sub.-- NODE line.
This error results because of the allowance of a state of one of the flip-flops 10 before the Q outputs have resolved to their quiescent states, i.e. low in this case. The gates of the N-channel pull-downs 26 are thus qualified to delay the Q outputs until the outputs have resolved to the state of the flip-flops. The ENABLE signal in FIG. 3 is a delayed version of the CLK or the external clock signal. The delay introduced by the representative pair of inverters 20 must be sufficient to guarantee stability of the Q outputs. Thus, for this circuit, the ENABLE signal must assert after all Q outputs of the flip-flops 10 have stabilized. This necessarily requires that the delay must be greater than the worst flip-flop CLK to Q output delay and must also incorporate some additional delay for safety. This delay is also increased by the AND gates 22 used to gate the inputs for the pull-down devices 26.
In addition to the above design considerations, the generation itself of the gating ENABLE signal mandates an additional delay. Because of the decoupling of the flip-flops and the generation of the ENABLE signal, it may be difficult to properly time the assertion of the ENABLE signal. To insure that the ENABLE signal follows all flip-flop outputs, an additional delay must be introduced which is greater than the anticipated worst case flip-flop output delay.
It is thus desirable to have a flip-flop that could be used in a dynamic logic function without generation of an external ENABLE signal and also without the need for the external AND gating logic or delay inverters and buffers.